The present invention relates to a transmission technique for an electronic device, and, particularly to a technique which is effectively applied to a chip input/output circuit system, which combines a driver circuit with a bus wiring system comprising a transmission line and a termination circuit matched with the line.
For example, a circuit structure as shown in FIG. 17, which shows a main part of an input/output circuit forming part of an electronic device, is considered to be a conventional technique which the present inventor has discussed in relation to a chip input/output circuit system. This input/output circuit comprises a differential driver 101 which converts an inputted digital signal into a complementary signal and transmits the signal; a differential receiver 102 which receives the complementary digital signal and outputs a digital signal corresponding to the inputted digital signal; and paired signal wires 103 which connect the differential driver 101 with the differential receiver 102. This circuit is arranged in order to transmit the complementary digital signal outputted from the differential driver 101 to the differential receiver 102.
In the input/output circuit of this electronic device, the differential driver 101 and the differential receiver 102 respectively comprise drivers 104 and 106, and inverters 105 and 107, each of which has a CMOS circuit structure comprising a pMOS transistor and an nMOS transistor. This structure operates complementarily, so that one of the transistors is turned on and the other is turned off when an inputted digital signal shifts from a low level to a high level, or from a high level to a low level. When an inputted digital signal thus shifts, by supplying complementary signal energy to the paired signal wires 103 from the differential driver 101a a complementary digital signal is transmitted to the differential receiver 102 through the paired signal wires 103.
Meanwhile, the following has been revealed as a result of studies by the present inventors with respect to an electronic device as described above. For example, if the paired signal wires in the electronic device described above are parallel wires having an equal length, which has a coupling coefficient close to 1, the paired signal wires can be structured as a transmission line whose electromagnetic field is substantially closed, and the complementary digital signal is transmitted in a mode (sub-TEM) close to TEM (Transversed Electromagnetic Mode) transmission so that the signal can be handled at high speed. This transmission line is one examples of a measure for transmitting a signal with high speed.
For example, suppose that a bus for exchanging signals in an electronic device is a transmission line. When a driver which supplies a signal sends a high-energy signal (which is a signal in a high state) to the bus, energy is required to raise the entire bus wire set at a ground level (which is a state of a low level) to a high level. This operation must be done before the driver transmits the signal to a receiver, if the signal rises at high speed.
Therefore, in the case where the rising time of a signal comes after the time required for supplying energy to the entire bus wire (which is the transmission delay time of the bus wires), energy supply from the driver is performed substantially in parallel to both the bus and the receiver, and there is almost no possibility that the receiver side can become aware of the existence of the bus. That is, this kind of serial work is a phenomenon which must be taken into consideration when the signal rising time is faster than the delay time of the bus wire. Naturally, it is the same with the opposite case of a transition to a low level, and such an operation to release the energy of the bus wire in a high-energy state is first required.
This kind of driver design need only enough energy to charge the load to the receiver when the rising of a signal is slower than the delay time of a bus. However, since an ordinary standard system now uses a high-speed signal, which has a shorter signal rising time than the delay time of a bus transmission line, it is more important to design how the energy should be supplied to the bus than to consider the characteristics of the receiver.
For example, an excellent receiver can sufficiently sense very weak signal energy and can change the state of the receiver itself, but does not consume the electric energy of signals. That is, an excellent receiver has a high direct-current resistance, for example, 1 Kxcexa9. In contrast, a bus transmission line has a characteristic impedance of 25 to 200xcexa9 and consumes energy which is greater by 1 or 2 digits than the receiver of the bus.
In this respect, the transmission time is 1.5 ns in the case where the length of a bus wire is set to 30 cm and the signal transmission speed is set to 2xc3x97108 m/s. Regardless of the position of the branch of the receiver, the period in which the signal flows through the entire length of the transmission line, for example, the period of 1.5 ns is a time for supplying the bus with energy. The driver must keep supplying energy during this period. Thus, the driver must have the ability to take the characteristic impedance as a load.
For example, in FIG. 18, which shows an equivalent circuit after a transition start of a signal immediately before the end of transmission of the signal to the termination end of a bus, if a differential driver 112 is connected to the start end of a transmission line 111, the bus must keep flowing a current during the period of 1.5 ns in the equivalent circuit shown in FIG. 18. In this respect, where the differential driver 112 has an internal resistance of 50xcexa9, a load resistance of 50xcexa9, and a Vdd voltage of 0.5 V, the resistance must be 50xcexa9 at 5 mA. From this value, the differential driver can be regarded as having a large drive ability. In this equivalent circuit, it is considered that the signal recognizes a termination end resistance from the instance when signal energy reaches a termination end, and the energy charge to the transmission line 111 is finished. Therefore, the load resistance 113 which is equivalent to the characteristic impedance of the transmission line 111, disappears, and the equivalent circuit then becomes as shown in FIG. 19.
In FIG. 19, suppose that the termination end resistor 114 now has a resistance of 50xcexa9, matched with the characteristic impedance of the bus, depending on the transmission line 111. Then, all of the energy is absorbed by this termination end resistor 114 and is discharged as a heat. As a result, no reflected energy returns. Even if a disturbance is caused due to a small parasitic element such as a branch or the like, no multiple reflection is prevented by the absorption described above. However, since the termination end resistor 114 is equal to the characteristic impedance of the bus, the differential driver 112 must keep current flowing of 5 mA as long as the high state continues. Therefore, the differential driver 112 which drives the transmission line 111, should desirably be a current switch circuit.
In addition, since the energy absorption by the termination end resistor 114 increases the electric power consumption of the bus wiring system, as a result, the energy absorption amount must be reduced. That is, in order to reduce the drive ability of the differential driver 112, a direct current resistance must be inserted so that the voltage is reduced. For example, if the voltage sensitivity of a differential receiver is increased, 50 mV or so can be achieved at the most. A current circuit or a differential circuit can be said to be a preferable driver. In principal, the signal amplitude can be reduced to as small as possible. This kind of bus structure is an ideal structure for a high-speed transmission line.
The present invention hence takes into consideration a bus structure as a transmission line, and has an object of providing an electronic device capable of high-speed signal transmission in a bus wiring system by specifying a circuit configuration of a driver circuit, and a characteristic impedance of a transmission line in an input/output circuit, which combines a driver circuit with a bus wiring system comprising transmission line and a termination end circuit matched with the transmission line.
The above-mentioned and other objects, in addition to a novel feature of the present invention, will be clearly understood from the description of the present specification and the drawings attached hitherto.
Representative aspects of the invention disclosed in the present application will be summarized in brief in the following discussion.
That is, An electronic device comprising: a transmission line; a termination circuit matched with said transmission line; a driver circuit for supplying a bus wiring system with a complementary signal, said driver circuit comprising said transmission line and said termination end circuit; a wiring board including said transmission line and said termination end circuit; and a first integrated circuit chip including said driver circuit and mounted on said wiring board. The transmission line is of a bus structure in which a line having characteristic impedance of 25xcexa9 or less, and having a structure comprising opposed paired wires, is wired such that said opposed paired wires are parallel to each other and have an equal length. As a result of this, it is possible to perform signal transmission at a high speed in a bus wiring system comprising a transmission line and a termination end circuit.
In this structure, the driver circuit is of a current switch type, and further, a pure resistor is connected in series with the driver circuit, thereby to form a ON-resistance which is equal to or higher than the characteristic impedance of the transmission line, or is preferably three times or more higher than the characteristic impedance of the transmission line.
In addition, in an electronic device according to the present invention, which relates to a one-way signal transmission structure from a first integrated circuit chip to a second integrated circuit chip, a second integrated circuit chip is connected to have a receiver circuit branched from and connected to the bus of the transmission line, and the receiver circuit has a high impedance of 1 Kxcexa9 or more. Further, when the receiver circuit is connected with a branch line having a transmission line structure of 4 mm or less, a pure resistor of 0.4 to 1 Kxcexa9 is connected in series with both of the opposed paired wires, at a branch portion of the branch line. Also, an insulating layer between the transmission line and the branch line has a thickness which is several times as large as the thickness of an insulating layer between the opposed paired wires of both the transmission line and the branch line. As a result of this, it is possible to perform, a one-way signal transmission at a high speed in from the first integrated circuit chip to the second integrated circuit chip.
Further, a power-source/ground line fanned out from the first integrated circuit including the driver circuit, is structured in a transmission line structure, and the transmission line of the power-source/ground line, comprising paired power-source wire and ground wire, has a characteristic impedance equal to or lower than the characteristic impedance of a signal line.
On the contrary, in an electronic device according to the present invention, which relates to one-way signal transmission from a second integrated circuit chip to a first integrated circuit chip, a second integrated circuit chip having a driver circuit of a current switch type is branched from and connected to a bus of the transmission line. The first integrated circuit chip has a receiver circuit of high impedance, and a complementary signal sent from the driver circuit of the second integrated circuit chip is received by the receiver circuit of the first integrated circuit chip. As a result of this, it is possible to perform a one-way signal transmission at a high speed from the second integrated circuit chip to the first integrated circuit chip.
In this structure, the signal flowing from the driver circuit to the transmission line flows with a xc2xd amplitude, each in directions toward the receiver circuit and the termination end circuit, and signal energy is totally reflected at the receiver circuit, thereby recovering an original amplitude, so that the receiver circuit operates normally, while signal energy flowing toward the termination end circuit is absorbed and erased.
Further, when the driver circuit is connected with a branch line having a transmission line structure, a chip of a bus transceiver gate for opening only a gate of an active branch wire is inserted at a branch portion of the branch line, and the branch line has a characteristic impedance which is lower than, or is preferably xc2xd of that of the transmission line. Further, the chip of the bus transceiver gate is structured in a collected chip structure in which a plurality of buses of the transmission line are respectively connected through gates of their own, and is arranged obliquely so as to follow above the power-source/ground line.
In addition, in an electronic device according to the present invention, which relates to a two-way signal transmission structure, in which the transmission from the first integrated circuit chip to the second integrated circuit chip, and the transmission from the second integrated circuit chip to the first integrated circuit chip are combined with each other. A second integrated circuit chip, having a receiver circuit and a driver circuit of a current switch type, is branched from and connected to a bus of the transmission line. The first integrated circuit chip has a driver circuit and a receiver circuit having high impedance, and a complementary signal is bidirectionally transferred between the driver and receiver circuits of the first integrated circuit chip and the receiver and driver circuits of the second integrated circuit chip, respectively. As a result of this, it is possible to perform two-way signal transmission at a high speed between the first and second integrated circuit chips.
In this structure, a circuit, in which a resistor and a gate which have high impedance during outputting, and which become a matched end during inputting, are connected in series to an exit of a combination circuit of the driver and receiver circuits of the first integrated circuit chip, is inserted between the input and output ends of the transmission line.
Further, when the receiver circuit and driver circuit of the second integrated circuit chip are connected with a branch line of a transmission line structure, a chip in which a bus transceiver gate and a high resistor are connected in parallel is inserted into a branch portion of the branch line, and the bus transceiver gate is opened when the first integrated circuit chip is outputting, and the bus transceiver gate is closed when the first integrated circuit chip is inputting, so that energy is supplied to the high resistor.
In addition, in an electronic device according to the present invention, which relates to matching of clock timings with the transmission line, when a plurality of second to n-th integrated circuit chips are branched from and connected to the transmission line, the driver circuit of the first integrated circuit chip has a control function, and a timing is taken, when signals of several pulses travel through the transmission line, in a manner in which the first integrated circuit chip measures echo times of the second to n-th integrated circuit chips. A return-way active clock is supplied to an integrated circuit chip which has the longest echo time, the integrated circuit chip which is supplied with the return-way active clock detects a forward-way clock signal, the first integrated circuit chip generates a return-way clock signal, based on the detected return-way clock signal, and the integrated circuit chip, which is supplied with the return-way active clock, generates a data strobe signal in return. As a result of this, it is possible to match the timings of the transmission line and the clock signal between the first integrated circuit chip and the second to n-th integrated circuit chips.
In this structure, a timing of data to be received by the first integrated circuit chip is known in a manner in which, only when a control signal from the first integrated circuit chip is a read command, an integrated circuit chip which generates a return-way clock signal again receives a data strobe signal from the transmission line and issues the data strobe signal as a delayed data strobe signal in return.
In particular, in the electronic device described above, the transmission line is a differential transmission line which transmits a differential complementary signal, the driver circuit is a differential driver circuit, and the receiver circuit is a differential receiver circuit. Although the apparatus is mainly characterized by a differential transmission line, it is needless to say that the present invention is applicable if the apparatus is replaced with a normal transmission line. In addition, the first integrated circuit chip is a controller chip, connected to a starting end of the transmission line, and the second integrated circuit chip is a memory/input/output interface chip.
Thus, according to the electronic device as described above, in an input/output circuit which combines a driver with a bus wiring system comprising a transmission line and a termination end circuit matched with the transmission line, attenuation of signal energy during transmission can be restricted, and electromagnetic interference between adjacent transmission lines can be restricted by specifying the driver as a current switch type, as well as the transmission lines as parallel wires having an equal length which have a characteristic impedance of 25xcexa9 or less. Therefore, it is possible to realize signal transmission at a higher speed in a bus wiring system.
Particularly, it is possible to improve signal transmission at a higher speed in one direction from a controller chip to a memory/input/output interface chip, or from a memory/input/output interface chip to a controller chip, or in both directions between a controller chip, which is connected to the starting end of a differential transmission line and has a differential driver and a memory/input/output interface chip, which is branched from and connected to the differential transmission line and has a differential receiver and a differential driver. It is therefore possible to provide an electronic device capable of realizing a high-speed transmission line in a bus wiring system.